<p>This paper designs a low temperature drift, low jitter on-chip oscillator applied to a 32-bit ultra-high precision, 38.4 kS/s sampling rate sigma-delta analog-to-digital converter (SD ADC). To enhance the flexibility of the design, three clock source mode configurations are provided to offer more functionality for the 32-bit ultra-precision SD ADC chip. Two chip pins are used to implement the mode switching, thereby reducing the number of pins required and improving system adaptability. Moreover, the on-chip clock needs to have extremely high quality to meet the requirements of the 32-bit ultra-high precision SD ADC. This paper effectively reduces clock jitter and temperature drift by employing a low temperature drift reference circuit and a calibrated switched capacitor circuit. Based on the TSMC 0.25 <InlineEquation ID="IEq1"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="34_2025_3069_Article_IEq1.gif" Format="GIF" Height="13" Rendition="HTML" Resolution="72" Type="Linedraw" Width="29" /> </InlineMediaObject> <EquationSource Format="TEX">$\upmu m$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mi mathvariant="normal">μ</mi> <mi>m</mi> </mrow> </math></EquationSource> </InlineEquation> CMOS process, the circuit is designed and simulated. Simulation results show that at the standard frequency of 7.3728 MHz, the maximum average clock jitter is 100 ps. The temperature drift in the range of − 55 to 125 <InlineEquation ID="IEq2"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="34_2025_3069_Article_IEq2.gif" Format="GIF" Height="7" Rendition="HTML" Resolution="72" Type="Linedraw" Width="9" /> </InlineMediaObject> <EquationSource Format="TEX">$^{\circ }$</EquationSource> <EquationSource Format="MATHML"><math> <mmultiscripts> <mrow /> <mrow /> <mo>∘</mo> </mmultiscripts> </math></EquationSource> </InlineEquation>C is only <InlineEquation ID="IEq3"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="34_2025_3069_Article_IEq3.gif" Format="GIF" Height="14" Rendition="HTML" Resolution="72" Type="Linedraw" Width="15" /> </InlineMediaObject> <EquationSource Format="TEX">$\Delta $</EquationSource> <EquationSource Format="MATHML"><math> <mi mathvariant="normal">Δ</mi> </math></EquationSource> </InlineEquation>1.2 MHz, and the total frequency variation under five process corners (CONER) is only <InlineEquation ID="IEq4"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="34_2025_3069_Article_IEq3.gif" Format="GIF" Height="14" Rendition="HTML" Resolution="72" Type="Linedraw" Width="15" /> </InlineMediaObject> <EquationSource Format="TEX">$\Delta $</EquationSource> <EquationSource Format="MATHML"><math> <mi mathvariant="normal">Δ</mi> </math></EquationSource> </InlineEquation>0.303 MHz. The clock process and temperature frequency error are less than 10%, and the clock process and temperature duty cycle error are also less than 10%. The power consumption is 372.9 <InlineEquation ID="IEq5"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="34_2025_3069_Article_IEq5.gif" Format="GIF" Height="17" Rendition="HTML" Resolution="72" Type="Linedraw" Width="31" /> </InlineMediaObject> <EquationSource Format="TEX">$\upmu W$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mi mathvariant="normal">μ</mi> <mi>W</mi> </mrow> </math></EquationSource> </InlineEquation>, with an operating current of only 113 <InlineEquation ID="IEq6"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="34_2025_3069_Article_IEq6.gif" Format="GIF" Height="17" Rendition="HTML" Resolution="72" Type="Linedraw" Width="28" /> </InlineMediaObject> <EquationSource Format="TEX">$\upmu A$</EquationSource> <EquationSource Format="MATHML"><math> <mrow> <mi mathvariant="normal">μ</mi> <mi>A</mi> </mrow> </math></EquationSource> </InlineEquation>.</p>

A Low Temperature Drift, Low Jitter On-Chip Oscillator Applied to 32-Bit Ultra-High Precision ADCs

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发表日期：

2025年4月5日

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Tao He,
Wenhao Hu,
Ping Li,
Hua Fan,
Fumei Liang,
Junjie Huang,
Haizhu Wang,
Chen Cui

摘要

This paper designs a low temperature drift, low jitter on-chip oscillator applied to a 32-bit ultra-high precision, 38.4 kS/s sampling rate sigma-delta analog-to-digital converter (SD ADC). To enhance the flexibility of the design, three clock source mode configurations are provided to offer more functionality for the 32-bit ultra-precision SD ADC chip. Two chip pins are used to implement the mode switching, thereby reducing the number of pins required and improving system adaptability. Moreover, the on-chip clock needs to have extremely high quality to meet the requirements of the 32-bit ultra-high precision SD ADC. This paper effectively reduces clock jitter and temperature drift by employing a low temperature drift reference circuit and a calibrated switched capacitor circuit. Based on the TSMC 0.25 $\upmu m$ $μ m$ CMOS process, the circuit is designed and simulated. Simulation results show that at the standard frequency of 7.3728 MHz, the maximum average clock jitter is 100 ps. The temperature drift in the range of − 55 to 125 $^{\circ }$ $^{\circ}$ C is only $\Delta $ $Δ$ 1.2 MHz, and the total frequency variation under five process corners (CONER) is only $\Delta $ $Δ$ 0.303 MHz. The clock process and temperature frequency error are less than 10%, and the clock process and temperature duty cycle error are also less than 10%. The power consumption is 372.9 $\upmu W$ $μ W$ , with an operating current of only 113 $\upmu A$ $μ A$ .