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<p>Computing-in-memory (CIM) technology has been developed to improve computer hardware efficiency for intelligent big data applications. An 8T-SRAM CIM macro with bitline leakage compensation ability is proposed in this study. In SRAM read mode, the proposed circuit solves the problem of read failure caused by bitline leakage current. In the write operation, the proposed circuit writes through the double-wordline, which can effectively improve the write static noise margin (WSNM) of the bitcell and reduce its write delay. When performing XNOR-and-accumulation (XAC) operations, the proposed circuit can effectively compensate the offset of the accumulated results due to bitline leakage current, thereby reducing output errors. In addition, this circuit can also be configured as binary content-addressable memory (BCAM) mode, and leakage compensation can be performed in this mode. A logic-AND sense amplifier (LASA) structure is also proposed, which can be applied in the SRAM read and BCAM modes. The proposed circuit is simulated in 55&#xa0;nm CMOS process, under 1.2&#xa0;V supply voltage. The proposed system demonstrates an energy efficiency of 62.7 TOPS/W, and effectively improves the anti-leakage ability of the array in all three modes.</p>

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8T-SRAM Computing-in-Memory Macro with Bitline Leakage Compensation

  • 期刊论文

  • 发表日期：

    2025年3月18日

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  • Chunyu Peng,
  • Junbo Chen,
  • Mengyi Zhao,
  • Wenjuan Lu,
  • Zhiting Lin,
  • Licai Hao,
  • Xin Li,
  • Chenghu Dai,
  • Xiulong Wu

摘要

Computing-in-memory (CIM) technology has been developed to improve computer hardware efficiency for intelligent big data applications. An 8T-SRAM CIM macro with bitline leakage compensation ability is proposed in this study. In SRAM read mode, the proposed circuit solves the problem of read failure caused by bitline leakage current. In the write operation, the proposed circuit writes through the double-wordline, which can effectively improve the write static noise margin (WSNM) of the bitcell and reduce its write delay. When performing XNOR-and-accumulation (XAC) operations, the proposed circuit can effectively compensate the offset of the accumulated results due to bitline leakage current, thereby reducing output errors. In addition, this circuit can also be configured as binary content-addressable memory (BCAM) mode, and leakage compensation can be performed in this mode. A logic-AND sense amplifier (LASA) structure is also proposed, which can be applied in the SRAM read and BCAM modes. The proposed circuit is simulated in 55 nm CMOS process, under 1.2 V supply voltage. The proposed system demonstrates an energy efficiency of 62.7 TOPS/W, and effectively improves the anti-leakage ability of the array in all three modes.