<p>A novel Symmetric Phase-Frequency Detector (SPFD) is introduced in this work. The symmetric design enhances the PFD’s performance, with optimization achieved through the Taguchi Design of Experiments and Pareto Analysis of Variance statistical techniques. The key design considerations for PFDs include phase noise, dead-zone, linearity, and frequency range. This circuit detects subtle phase deviations at higher frequencies and eliminates the dead zone. It operates at a peak frequency of 9.47 GHz and exhibits a phase noise of <InlineEquation ID="IEq1"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="34_2025_3030_Article_IEq1.gif" Format="GIF" Height="13" Rendition="HTML" Resolution="72" Type="Linedraw" Width="19" /> </InlineMediaObject> <EquationSource Format="TEX">$-$</EquationSource> <EquationSource Format="MATHML"><math> <mo>-</mo> </math></EquationSource> </InlineEquation>159.63 dBc/Hz at a 1 MHz offset from the carrier. Implemented using GPDK 45nm CMOS technology and developed in the Cadence Virtuoso environment, this circuit shows notable improvements over prior designs, with a power consumption of 2.76 <InlineEquation ID="IEq2"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="34_2025_3030_Article_IEq2.gif" Format="GIF" Height="12" Rendition="HTML" Resolution="72" Type="Linedraw" Width="15" /> </InlineMediaObject> <EquationSource Format="TEX">$\mu $</EquationSource> <EquationSource Format="MATHML"><math> <mi>μ</mi> </math></EquationSource> </InlineEquation>W at a 1.1 V power supply. The circuit layout, designed in Virtuoso Layout XL, covers an area of 33.69 <InlineEquation ID="IEq3"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="34_2025_3030_Article_IEq2.gif" Format="GIF" Height="12" Rendition="HTML" Resolution="72" Type="Linedraw" Width="15" /> </InlineMediaObject> <EquationSource Format="TEX">$\mu $</EquationSource> <EquationSource Format="MATHML"><math> <mi>μ</mi> </math></EquationSource> </InlineEquation> <InlineEquation ID="IEq4"> <InlineMediaObject> <ImageObject Color="BlackWhite" FileRef="34_2025_3030_Article_IEq4.gif" Format="GIF" Height="16" Rendition="HTML" Resolution="72" Type="Linedraw" Width="22" /> </InlineMediaObject> <EquationSource Format="TEX">$m^2$</EquationSource> <EquationSource Format="MATHML"><math> <msup> <mi>m</mi> <mn>2</mn> </msup> </math></EquationSource> </InlineEquation>. The proposed SPFD has undergone PVT and Monte Carlo analyses, and post-layout simulations have confirmed the results obtained from pre-layout simulations.</p>

Design and Optimization of a Symmetrical Phase-Frequency Detector (SPFD) Through Statistical Techniques

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发表日期：

2025年2月11日

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Jyoti Sharma,
Archana Singhal,
Tarun Varma,
Dharmendar Boolchandani

摘要

A novel Symmetric Phase-Frequency Detector (SPFD) is introduced in this work. The symmetric design enhances the PFD’s performance, with optimization achieved through the Taguchi Design of Experiments and Pareto Analysis of Variance statistical techniques. The key design considerations for PFDs include phase noise, dead-zone, linearity, and frequency range. This circuit detects subtle phase deviations at higher frequencies and eliminates the dead zone. It operates at a peak frequency of 9.47 GHz and exhibits a phase noise of $-$ $-$ 159.63 dBc/Hz at a 1 MHz offset from the carrier. Implemented using GPDK 45nm CMOS technology and developed in the Cadence Virtuoso environment, this circuit shows notable improvements over prior designs, with a power consumption of 2.76 $\mu $ $μ$ W at a 1.1 V power supply. The circuit layout, designed in Virtuoso Layout XL, covers an area of 33.69 $\mu $ $μ$ $m^2$ $m^{2}$ . The proposed SPFD has undergone PVT and Monte Carlo analyses, and post-layout simulations have confirmed the results obtained from pre-layout simulations.