The efficacy of the Directional Median Filter (DMF) in restoring images corrupted by impulse noise has been demonstrated in various image processing applications. Conversely, its complex algorithm presents challenges to its hardware implementation. This paper discusses the \(5 \times 5\) window DMF methodology, emphasizing improvements in image edge pixels preservation. This modification aims to address the issue of pixel noise at the edge. Furthermore, we suggest a clock-gated hardware implementation of the modified DMF. We implement the design using NanGate 45 nm Technology and Virtex UltraScale FPGA. To ensure the validity of our design, we developed a software model of the suggested DMF in MATLAB, which was used to verify the algorithm’s functionality and performance against noise-corrupted images. Despite the hardware implementation involving an approximation for computationally intensive operations such as division and square root, the accuracy of the hardware results remains comparable to state-of-the-art filtration methods. The suggested hardware implementation is highly efficient in terms of power and energy consumption. In comparison to the state-of-the-art, the power consumption is reduced by approximately 45% to 60%, while energy consumption is decreased by 30–50%. Consequently, the design is well-suited for low-energy applications.
