A Multiply-by-Two Switched-Capacitor Amplifier with Reduced Sensitivity to Capacitive Mismatch

This paper proposes a switched-capacitor amplifier with reduced sensitivity to capacitive mismatch for pipelined and algorithmic ADCs having an inter stage gain of two. It uses four operation phases to generate the residue voltage that is less sensitive to capacitive mismatch. An improvement in the proposed switched-capacitor amplifier is obtained without additional area or power requirements. The proposed switched-capacitor amplifier is designed and simulated in 65 nm CMOS process. The performance of proposed design is verified through post-layout simulations considering different environmental conditions. The design occupies an area of 58  \(\upmu \textrm{m}\) $\mathrm{\mu }\text{m}$ \(\times \) $\times$ 60  \(\upmu \textrm{m}\) $\mathrm{\mu }\text{m}$ . It consumes 256  \(\upmu \textrm{W}\) $\mathrm{\mu }\text{W}$ of power at 1.2 V supply.