A 1–6 GHz Reconfigurable Low-IF Harmonic Mixing Receiver with 2.2–2.6 dB NF and 33–38 dB IMRR in 65 nm CMOS for Wireless Applications

In this work, a 1–6 GHz reconfigurable low-IF receiver that integrates a wideband pseudo-differential reactance cancelling LNA, a fully-differential four-path passive mixer, a transimpedance amplifier (TIA), and a polyphase filter (PPF) into a single cell is designed in 65 nm CMOS process. The second-order harmonic mixing is introduced in the four-path mixer to achieve the desired performance upto higher RF frequency range with lower power dissipation. The wide band input matching without any external component and high RF gain are achieved via optimizing the front-end reactance cancelling LNA. The later stage incorporates the baseband TIA for gain boosting and PPF for enhanced image rejection. The four-path mixer is driven by a 25 % duty cycle clock generated using the on-chip PPF and a combinational circuit. Furthermore, complex feedback is integrated at the TIA output to enable the shifting of the gain and \(\varvec{S_{11}}\) ${\mathit{S}}_{\mathbf{11}}$ peak. The design also incorporates switches for high-side or low-side injection choice of the desired signal. The generated baseband signal is immediately filtered by three stage PPF providing image rejection and channel selection. The proposed reconfigurable low-IF receiver achieves \(-\) $-$ 10 dB of \(\varvec{S_{11}}\) ${\mathit{S}}_{\mathbf{11}}$ , 59.5–54.1 dB of gain and 2.2–2.6 dB of noise figure (NF) at a minimal signal path power dissipation of 10.26 mW and a clock power consumption of 0.7 mW per GHz for frequency range of 1–6 GHz. Additionally, an image rejection ratio (IMRR) of 33–38 dB is attained across the entire bandwidth of 80 MHz at LO of 1 GHz. Most of the performance metrics are comparable with the state-of-the-art.