A Power-Efficient Gaussian Filter Architecture Using Adder Compressors for Edge Detection Application

Edge detection is a ubiquitous operation and has found widespread use in computer vision applications. This algorithm’s fundamental module is the Gaussian filtering block, which is computation-intensive since it involves power-hungry addition operations. Imprecise computations can be carried out in these filter modules to reduce power consumption since it is an error-resilient application. This work aims to reduce the computation complexity in the edge detection module, thereby power consumption by using novel compressor-based Gaussian filter architecture. Further, improvement in power and power-delay product has been achieved with new proposed approximate compressors. Error and hardware analyses were carried out to prove that the Gaussian filter when implemented using the proposed design, achieves a better quality-effort trade-off compared to existing schemes. Hardware results indicate an improvement in power and power-delay product up to 34% and 38.5%, respectively, without compromising PSNR compared to similar work published previously.