FPGA-specific efficient LUT-based designs for the digit-serial multiplication over GF \((2^m)\) are presented. It is shown that composite logic could be mapped to LUTs directly using the input bits as addresses to reduce FPGA resources and delay over conventional gate-oriented designs. We show that the MSD-first digit-serial multiplication could be decomposed into suitable blocks and mapped efficiently into the FPGA LUTs. We have explored different reordering and decomposition of logic operations involved in MSD-first multiplication to reduce the computation time and energy consumption. We have coded the proposed designs, conventional LSD-first, and MSD-first designs using VHDL for \(m=163\) and 233 and implemented using Xilinx Vivado v.2023.2 for various digit sizes. We have studied the performance of all these designs extensively and presented them in this paper. Our proposed designs require less delay and less dynamic power than the conventional MSD-first and LSD-first designs. It is found that computation time falls steadily but the energy per multiplication (EPM) and slice delay product (SDP) increase with the digit size. Therefore, large digit sizes should be used when fast multiplication is required. Proposed designs offer savings of SDP and EPM of 35.37% and 49.75%, respectively, on average, for \(m=163\) and \(m=233\) ; and digit size \(w=4, 8,\) and 16 over the LSD-first design, and similar savings of 41.19% and 36.70%, over the conventional MSD-first design.
