Heuristic Analysis of Digital Down Converter Design for Software-Defined Radio Applications

This paper presents a new method for implementing an efficient digital down converter (DDC) using a field-programmable gate array (FPGA) for software-defined radio standards. The DDC consists of a pipeline coordinate rotation digital computer (CORDIC) rotator to produce a complex waveform, followed by a cascade of multi-stage cascaded integrator comb (CIC) filter and a polyphase transposed finite impulse response (PTFIR) filter to reduce large sample rates with lowpass filtering. The canonical signed-digit encoding in the CORDIC architecture reduces many adders and shifters. The CIC filter works with a new polynomial function that reduces passband droop by 34.29% and stopband ripple by 41.35% when compared with the traditional approach. The proposed PTFIR filter considerably reduces delay units. Again, the adder is the basic functional unit of the DDC structure. In this brief, each component of the DDC is examined with hybrid parallel prefix adders. The presented HPPA utilizes less critical path delay and less area when compared to conventional structures. The design has been simulated in the Xilinx Vivado 2022.1, which implements the FPGA Kintex-7 device. According to comparison results, the proposed DDC reduces approximately 30.51% of the area-delay product and 29.32% of the power-delay product associated with the best design. A verification test certifies the functionality of the prototype architecture.