A Novel 571.78 MHz–11.07 GHz Tuning Range Differential Ring Oscillator Application in a PLL Frequency Synthesizer with 895 ns Lock Time

This paper introduces a 3-stage differential ring oscillator (DRO) with a broad tuning range spanning from 571.78 MHz to 11.07 GHz. A delay circuit utilizing dual control voltages is proposed for the 3-stage DRO. One control voltage sets the frequency range from 571.78 MHz to 4.38 GHz, while another control voltage establishes a frequency range from 3.97 to 11.07 GHz. The DRO exhibits total harmonic distortion of 10.26%, phase noise of \(-\) $-$ 91.98 dBc/Hz at 1 MHz and \(-\) $-$ 117.3 dBc/Hz at 10 MHz offset. DRO circuit’s robustness is performed with the help of Monte Carlo simulation and process, voltage, and temperature variation. The figure of merit measured for this DRO is \(-\) $-$ 171.39 dBc/Hz and it occupies an area of 0.0017 mm². The DRO’s oscillation frequency is also analyzed through post-layout simulation results. The proposed DRO shows the widest tuning range in comparison to the current literature. The PLL frequency synthesizer is implemented utilizing the proposed DRO circuit and it achieved a less locking time of 835 ns at an output frequency of 3.2 GHz. The synthesizer is also achieved low jitter and low reference spur magnitude. DRO and PLL frequency synthesizer circuits are designed and simulated with a 1.8 V supply voltage using 0.18 \(\mu \) $\mu$ m CMOS technology.