FPGA Implementation and Performance Analysis of Parallel Prefix Structures for Modular Adders Design

Today’s consumer electronics market is the hub of portable devices claiming low power consumption and less area with high speed of processing. Processors are the heart of all the computations taking place in these devices. The data path elements, inclusive of binary and modular adders in a processor perform these computational operations. Parallel prefix adder, a variant of conventional carry look ahead binary adder promising fast arithmetic operations has been the point of interest for researchers since last decade. FPGA based synthesis and implementation are the most preferred solutions among those proposed in the last few years. Selecting an adder with the appropriate characteristics is essential to simplify the processor's operation and minimize its complexity. Performance measures including power dissipation, implementation area, and critical path delay need to be exhaustively analysed as benchmarks to assess the trade-offs that these adder circuits provide. However, existing literature lacks in providing a comparative performance analysis of popular parallel prefix adders. This paper displays a novel juxtaposition of five popular radix-2 parallel prefix adders at variable data path sizes ranging from 8 to 32 bits. The PPA tree topologies investigated in this paper are coded using VHDL description language and synthesized using VIVADO 2014.2 tool targeted to Zynq family FPGAs device (xc7z020clg484-1). Detailed analysis is performed for each structure in terms of total path delay, design implementation area, hardware utilization and the total power consumption. This paper presents a thorough evaluation of various parallel prefix adders, which simplifies the laborious task of choosing the optimal adder circuit. A disquisition on parallel prefix adders presented in this paper is benchmarked against other state-of-the-art published works. It can be inferred from the literature survey that the comparative analysis presented in this paper is more comprehensive, covering all aspects of comparison, than the previously published works.