In this paper, we propose an energy-efficient design of architecture for digit-serial multiplication over generic GF( \(2^m\) ), which could be used for different fields as and when required and to enhance the security by changing the fields. An efficient input scheduling scheme is proposed to reduce the required number of input pins and a digit extraction circuit for digit-serial multiplication. Besides, to reduce the dynamic power consumption, we have proposed a simple technique using an array of m AND gates that minimizes the output bit-switching. To study the impact of digit size, the digit-serial multipliers for \(m=163\) and 233 are synthesised by Xilinx Vivado for FPGA implementation. It is found that the required number of slices, power consumption, and energy per multiplication increase while the computational delay falls with the increase in digit size. Therefore, larger digit sizes could be considered only when fast multiplication is necessary. The array of AND gates for output bit control helps in reducing the dynamic power consumption and energy per multiplication, respectively, by 50.4% and 57.7% for \(m=163\) and \(49.8\%\) and \(51.8\%\) , for \(m=233\) , on average, for different digit sizes over the conventional least-significant-digit-first design.
