Design of an Area Efficient and High-Performance Adder with a Novel Sum Generator

One of the major study areas in VLSI system design is the creation of an area-efficient, high-speed adder. So this paper focused on an effective adder design as an Area Effective Novel Sum Generator (AENSG) to make it suitable for real-time applications. The major operations involved in this adder are Brent Kung addition, group kill and generate (KG) signal generation, Kill Generate Propagate (KGP) signal generation, and various sum generation categories. In the sum-generating block, AENSG is utilized to minimize the space by a reduction in the number of logic gates. Xilinx ISE 13.1 is used to synthesize and validate the suggested adder design. The 64-bit AENSG adder has 37.98%, 9.09% lesser number of logic gates and 34.81%, 28.40% lesser delay when compared with PPF/CSSA_4 and hybrid adder respectively.