A Low-Energy, Stable, Single-Bitline Accessed FinFET 9T-SRAM

SRAMs, the go-to choice for system-on-chips nowadays, suffer from high power consumption and unstable behavior in nanoscale CMOS technology. Consequently, we observe the emergence of troublesome short-channel effects (SCEs), necessitating the utilization of innovative nano-devices. Combining its attractive features, including reduced SCEs and leakage, the fin-shaped field-effect transistor (FinFET) shines as a skillful replacement for CMOS, skillfully tackling those injurious problems. This paper presents a near-threshold single-bitline 9T (SB9T) SRAM cell, with a primary focus on enhancing stability and energy efficiency. The SB9T SRAM cell integrates a read-assist scheme and a feedback-cutting technique to enhance read stability and writability. By conducting simulations utilizing a 7-nm FinFET technology and operating at a voltage of 0.5 V, the SB9T SRAM cell demonstrates remarkable performance advantages when compared to existing designs. Specifically, in comparison to the conventional 6T cell, the SB9T SRAM cell achieves an improvement of 1.86 × in read stability and 2.41 × in writability. Additionally, the SB9T SRAM cell minimizes power dissipation from leakage by at least 8.73% and enhances write energy efficiency by a minimum of 4.84%. It should be noted that although the SB9T SRAM cell consumes 1.03 × more read energy than the conventional 8T cell, it still surpasses alternative designs by reducing read energy consumption by at least 4.86%.